R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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4.5.3. Deskew Channel

In PIPE Direct mode, the PHY wrapper removes any lane-to-lane skew introduced while crossing the EMIB. A dedicated deskew marker is used for detecting and compensating for any multi-lane skew introduced by EMIB. The deskew logic can account for a maximum of up to 3 cycles of parallel skew. After a cold/warm/hot reset or CvP update, the deskew process will start.

The user application logic needs to send a deskew marker every 16 clock cycles for the purpose of deskewing the data on the EMIB channels. The PHY deskew logic will run the deskew process every time it receives the deskew marker.

Table 79.  EMIB TX Deskew Grouping for R-tile Topologies
PIPE Direct Tx Deskew Bundle Octet 1 Octet 0
Lane 15 Lane 14 Lane 13 Lane 12 Lane 11 Lane 10 Lane 9 Lane 8 Lane 7 Lane 6 Lane 5 Lane 4 Lane 3 Lane 2 Lane 1 Lane 0
1X16 Octet1_Dsk_0 Octet0_Dsk_0
2X8 Octet1_Dsk_0 Octet0_Dsk_0
4X4 Octet1_Dsk_2 Octet1_Dsk_0 Octet0_Dsk_2 Octet0_Dsk_0
8X2 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
16X1 No Tx Deskew
2X4; 1X8 Octet1_Dsk_2 Octet1_Dsk_0 Octet0_Dsk_0
4X2; 1X8 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 Octet0_Dsk_0
8X1; 1X8 No Tx Deskew Octet0_Dsk_0
1X8; 2X4 Octet1_Dsk_0 Octet0_Dsk_2 Octet0_Dsk_0
4X2; 2X4 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 Octet0_Dsk_2 Octet0_Dsk_0
8X1; 2X4 No Tx Deskew Octet0_Dsk_0 Octet0_Dsk_0
1X8; 4X2 Octet1_Dsk_0 Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
2X4; 4X2 Octet1_Dsk_2 Octet1_Dsk_0 Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
8X1; 4X2 No Tx Deskew Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
1X8; 8X1 Octet1_Dsk_0 No Tx Deskew
2X4; 8X1 Octet1_Dsk_2 Octet1_Dsk_0 No Tx Deskew
4X2; 8X1 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 No Tx Deskew

MAC to PHY (M2P) Signals

Table 80.  PIPE Direct EMIB Control Deskew Channel M2P Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_deskew_clear_0/1/2/3_i Input When asserted, the current tx_dsk_eval_done and tx_dsk_status are cleared. A new deskew evaluation is expected after the current status is cleared. This signal is asserted for two clock cycles. pipe_direct_pld_tx_clk_out_o

PHY to MAC (P2M) Signals

Table 81.  PIPE Direct EMIB Control Deskew Channel P2M Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_txdeskewmarker_i Input Tx Deskew marker used to deskew EMIB routings per bundle mode. This is a simple repeating pulse that provides a protocol-agnostic mechanism to detect EMIB channel skew and perform alignment. The marker fans out and appears on all bundle channels simultaneously once every 16 clock cycles. The deskew module looks for the deskew marker from each EMIB channel and adds delays on the early channels to compensate for the delays of the late channels. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_active_chans_o Output Indicates which channels received a deskew marker. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_monitor_err_o Output

Value is latched upon an error, and held until the state machine is restarted via i_dsk_clear or async reset.

Monitor this signal only after 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles following the assertion of octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o.

pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_monitor_err_status_[3:0]_o Output

Indicates a deskew monitor error.

Monitor this signal only after 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles following the assertion of octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o.

pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_status_[3:0]_o Output

Indicates the deskew evaluation result.

Monitor this signal only after 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles following the assertion of octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o.

Note: octet#_pipe_direct_phy_dsk_status should be monitored only after octet#_pipe_direct_phy_dsk_valid is asserted.
pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_valid_[3:0]_o Output

Indicates the deskew operation status.

When using x16, the octet#_pipe_direct_phy_dsk_valid_o from each of the octets must be ANDed together by the user logic.

pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o Output Indicates the deskew process is complete. This signal is for debugging purpose. When using x16, the octet#_pipe_direct_phy_dsk_eval_done_o from each of the octets must be ANDed together by the user logic. pipe_direct_pld_tx_clk_out_o
To use the deskew interface, follow these steps:
  1. The controller in the application logic sends the deskew marker for each lane of the bundle every 16 pclk (pipe_direct_pld_tx_clk_out_o) cycles using the signal ln*_pipe_direct_txdeskewmarker_i.
  2. After the data from the EMIB is deskewed, octet*_pipe_direct_phy_dsk_valid_o is asserted, indicating deskew done status.
    Note: (*) When using x16, the octet*_pipe_direct_phy_dsk_valid_o from each of the octets must be ANDed together.
  3. In addition to the octet*_pipe_direct_phy_dsk_valid_o signals, the PIPE interface provides octet*_pipe_direct_phy_dsk_eval_done_o and octet*_pipe_direct_phy_dsk_status_*_o signals to show the details of the deskew status.
    Note: (#) These signals are for debugging purposes only. The user application logic should rely only on the octet*_pipe_direct_phy_dsk_valid_o signals.
  4. The octet*_pipe_direct_deskew_clear_i signals on both octets can be used to clear the current deskew state to allow additional deskew evaluations. When using x16, the octet*_pipe_direct_deskew_clear_i for each of the octets must be used.
  5. After the pulse on octet*_pipe_direct_deskew_clear_i, the deskew state on octet*_pipe_direct_phy_dsk_monitor_err_o bus is cleared.

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