R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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1.6. IP Core Support Levels

The following table shows the support levels of the R-tile Avalon® streaming IP core in Intel® Agilex™ devices.

Table 8.  R-tile Avalon streaming IP for PCIe Support Matrix for Intel® Agilex™ DevicesSupport level keys: S = simulation, C = compilation, T = timing, H = hardware, N/A = configuration not supported
Configuration PCIe IP Support
EP RP BP
16-channel PIPE Direct N/A N/A N/A
Gen5 x16 1024-bit SCT SCT SCT
Gen4 x16 1024-bit SCT SCT SCT
Gen3 x16 1024-bit SCT SCT SCT
Gen5 x8/x8 512-bit SCT SCT SCT
Gen4 x8/x8 512-bit SCT SCT SCT
Gen3 x8/x8 512-bit SCT SCT SCT
Gen5 x4/x4/x4 256-bit SCT SCT SCT
Gen4 x4/x4/x4 256-bit SCT SCT SCT
Gen3 x4/x4/x4 256-bit SCT SCT SCT
Note: Port 2 is not available in x4 mode in the 21.4 release of Intel® Quartus® Prime, but may be available in a future release.
Note: PIO design examples are available only in the x16 and 2x8 EP modes in the 21.4 release of Intel® Quartus® Prime.

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