R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)

The capability register identifies that this is a vendor-specific capability. It also identifies the structure type.

Table 36.  VirtIO PCI Configuration Access Capability Register
Bit Location Description Access Type Default Value
31:24 Configuration Type RO 0x05
23:16 Capability Length RO 0x14
15:8 Next Capability Pointer RO 0x00
7:0 Capability ID RO 0x09