7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
|Document Version||Intel® Quartus® Prime Version||IP Version||Changes|
Added the new section BTI Protection Mode.
Updated the Completion Buffer Size section to show the correct buffer sizes. Also added examples showing the amount of Completion buffer entries consumed for Memory Read requests. Finally, added a suggested flow for the Application logic to track the completion buffer entries and based on this, schedule Non-Posted (NP) requests to the R-Tile Avalon® Streaming Intel FPGA IP for PCI Express.
Updated the text descriptions and timing waveforms for the Avalon Streaming RX Interface and the Avalon Streaming TX Interface to show how the user application logic can properly use these interfaces.
Updated the signal descriptions and timing waveforms for the Deskew Channel section to show how the user application logic can properly use this interface.
|2021.10.06||21.3||3.0.0||Removed the section ECRC due to missing information on the register offsets for the ECRC or LCRC counters.|
Updated the block diagrams in the PCI Express Mode and PIPE Direct Mode sections to match the interface signals on the 21.3 block symbol for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express.
Added a Note to the Avalon Streaming TX Interface section stating that for this interface, the SOP can only be sent on segments 0 and 2.
Added the Root Port Enumeration Appendix chapter.
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