2.3. PCIe Hard IP Mode
In this mode, the four cores (one x16 core, one x8 core and two x4 cores) in the PCIe Hard IP can be configured to support the following topologies:
|Configuration Mode||Native IP Mode||Endpoint (EP) / Root Port (RP) / TLP Bypass (BP)||Active Cores|
|Configuration Mode 0||Gen3 x16 or Gen4 x16 or Gen5 x16||EP/RP/BP||x16|
|Configuration Mode 1||Gen3 x8/Gen3 x8 or Gen4 x8/Gen4 x8 or Gen5 x8/Gen5 x8||EP/RP/BP||x16, x8|
|Configuration Mode 2||Gen3 x4/Gen3 x4/Gen3 x4/Gen3 x4 or Gen4 x4/Gen4 x4/Gen4 x4/Gen4 x4 or Gen5 x4/Gen5 x4/Gen5 x4/Gen5 x4||EP/RP/BP||x16, x8, x4_0, x4_1|
|Configuration Mode 3||PIPE Direct (with a maximum of 16 channels)||N/A||None|
In Configuration Mode 0, only the x16 core is active, and it operates in x16 mode (in Gen3, Gen4 or Gen5).
Each of the cores has its own Avalon® -ST interface to the user logic. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the configuration modes.
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