R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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1.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the R-tile Avalon® streaming IP core supports.

Table 6.   Intel® Agilex™ Recommended FPGA Fabric Speed Grades for All Avalon Streaming Widths and Frequencies

Lane Rate

Link Width

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Gen5 x4 400 - 500 -1, -2
x8 400 - 500 -1, -2
x16 400 - 500 -1, -2
Gen4 x4 250 - 300 -1, -2, -3
x8

250 - 300

-1, -2, -3
x16

250 - 300

-1, -2
Gen3 x4 250 - 300 -1, -2, -3
x8 250 - 300 -1, -2, -3
x16 250 - 300 -1, -2, -3

PIPE Direct

16-channel 500 -1, -2
Note: The application clock frequency range is divided into steppings of 25 MHz, selectable in the IP Parameter Editor.

The following table shows the typical resource utilization information for selected configurations.

The resource usage is based on the Avalon® streaming IP core top-level entity (intel_rtile_pcie_ast) that includes IP core soft logic implemented in the FPGA fabric.

Table 7.  Resource Utilization Information for the R-tile Avalon® Streaming IP in the PIO Design Example
Design Example Used Link Configuration Device Family ALMs M20Ks Dedicated Logic Registers
Programmed I/O (PIO) Gen5 x16 Intel® Agilex™ 11721 0 32819
Programmed I/O (PIO) Gen4 x16 Intel® Agilex™ 11617 0 28127
Programmed I/O (PIO) Gen3 x16 Intel® Agilex™ 11617 0 28127
Programmed I/O (PIO) 16-channel PIPE Direct Intel® Agilex™ 2257 0 1836

For more details on the R-tile Avalon® Streaming design example, refer to R-tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide.

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