R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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4.5.2. Message Channel

This interface is used for PHY (P)-MAC (M) communication, using the P2M and M2P unidirectional 8-bit signals per lane. This interface serves to reduce the number of dedicated signals for implementations like link equalization, lane margining etc.

Table 78.  PIPE Direct EMIB Control Message Channel M2P/P2M Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_m2p_messagebus_i[7:0] Input Low Pin Count Message Interface from MAC to PHY. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_p2m_messagebus_o[7:0] Output Low Pin Count Message Interface from PHY to MAC. pipe_direct_pld_tx_clk_out_o
Note:
The PHY does not support querying the FS/LS/Preset/Coefficient values via the PIPE interface. The controller can use the following values for the PHY:
  • FS = 48, LF = 16 for Gen3/Gen4/Gen5
  • For Gen3/Gen5, {c-1, c0, c+1 = preset} = {8/40/0 = P9}
  • For Gen4, {c-1, c0, c+1 = preset} = {0/42/6 = P3}

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