R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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4.5. PIPE Direct Mode

In the PIPE Direct mode, either one or both of the PCIe and CXL controller stacks are entirely bypassed, and the PIPE SerDes mode interface is exported across the Embedded Multi-die Interconnect Bridge (EMIB) to the FPGA fabric. This mode allows you to implement your own custom controllers in soft IP.

In PIPE Direct mode, each entire octet must be configured to the same base mode setting (Gen5 capable). All per-lane variations are configured through the PIPE Rate[2:0] and Powerdown[1:0] control settings, which are independent per-lane.

Note: In the 21.4 release of Intel® Quartus® Prime, the PIPE Direct mode does not support design example or testbench generation.
Figure 35. R-tile Top-Level Block Diagram in PIPE Direct Mode

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