R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/13/2021
Public

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4.4.8.2. Endpoint D3Hot Exit

The Power Management Capability register must enable D3Hot PME_Support. In addition, software must set the PME_en bit in the Power Management Control and Status register.

Application logic needs to assert apps_pm_xmt_pme_i signal to initiate the exit from D3.

Figure 33. Timing Diagram for D3Hot Exit

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