Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

7.3. RX MAC Registers

Table 26.  RX MAC Registers
Addr Name Description Reset Access
0x500 RXMAC_REVID

RX MAC revision ID for Low Latency E-Tile 40G EthernetIP core.

0x0627 2016 RO
0x501 RXMAC_SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x502 RXMAC_NAME_0

First 4 characters of IP core variation identifier string, "40gMACRxCSR".

0x3430 674D

RO

0x503 RXMAC_NAME_1 Next 4 characters of IP core variation identifier string, "ACRx". 0x4143 5278

RO

0x504 RXMAC_NAME_2 Final 4 characters of IP core variation identifier string, "0CSR". The "0" is unprintable. 0x0043 5352

RO

0x506 MAX_RX_SIZE_CONFIG Specifies the maximum frame length available. The MAC asserts when the length of the received frame exceeds the value of this register. 0xXXXX 2580 7

RW

0x507 MAC_CRC_CONFIG The RX CRC forwarding configuration register. The following encodings are defined:
  • 1'b0: Remove RX CRC, do not forward it to the RX client interface
  • 1'b1: Retain RX CRC, forward it to the RX client interface
In either case, the IP core checks the incoming RX CRC and flags errors.
31'hX1'b0 7

RW

0x508 LINK_FAULT

Link Fault Status Register.

For unidirectional Link Fault, implements IEEE 802.3 Ethernet Clause 66.

30'hX2'b00 7

RO

0x50A RX_MAC_CONTROL RX MAC Control Register.
  • Bit [1]: VLAN detection disabled. This bit is deasserted by default implying VLAN detection is enabled.
30'h0_2'b0X 7 RW
7 X means "Don't Care".

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