Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench

Intel® provides a compilation-only example design and a testbench with most variations of the Low Latency E-Tile 40G Ethernet IP core.

To generate the testbench, you must first set the parameter values for the IP core variation you intend to generate. If you do not set the parameter values identically, the testbench you generate might not exercise the IP core variation you generate. If your IP core variation does not meet the criteria for a testbench, the generation process does not create a testbench.

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