Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

1.2.1. Device Family Support

Table 1.   Intel FPGA IP Core Device Support Levels

Device Support Level

Definition

Advance

The IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (datapath width, burst depth, I/O standards tradeoffs).

Preliminary

The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.

Final

The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 2.   Low Latency E-Tile 40G Ethernet IP Core Device Family SupportShows the level of support offered by the Low Latency E-Tile 40G Ethernet IP core for each Intel FPGA device family.

Device Family

Support

Intel® Stratix® 10

Preliminary

Intel® Agilex™

Preliminary

Other device families

No support

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