Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Document Table of Contents

5. Reset

Control and Status registers control three parallel soft resets. These soft resets are not self-clearing. Software clears them by writing to the appropriate register. In addition, the IP core has three hard reset signals.

Asserting the external hard reset csr_rst_n returns all Control and Status registers to their original values, except the statistics counters. An additional dedicated reset signal resets the transceiver reconfiguration interface.

Figure 10. Conceptual Overview of General IP Core Reset Logic The three hard resets are top-level ports. The three soft resets are internal signals which are outputs of the PHY_CONFIG register. Software writes the appropriate bit of the PHY_CONFIG to assert a soft reset.

The general reset signals reset the following functions:

  • soft_tx_rst, tx_rst_n: Resets the IP core in the TX direction. Resets the TX PCS and TX MAC. This reset leads to deassertion of the tx_lanes_stable output signal.
  • soft_rx_rst, rx_rst_n: Resets the IP core in the RX direction. Resets the RX PCS and RX MAC. This reset leads to deassertion of the rx_pcs_ready output signal.
  • sys_rst, csr_rst_n: Resets the IP core. Resets the TX and RX MACs, PCS, and transceivers.
    Note: csr_rst_n resets the Control and Status registers, except the statistics counters. sys_rst does not reset any Control and Status registers.
    This reset leads to deassertion of the tx_lanes_stable and rx_pcs_ready output signals.

In addition, the synchronous reconfig_reset signal resets the IP core transceiver reconfiguration interface, an Avalon® memory-mapped interface. Associated clock is the reconfig_clk, which clocks the transceiver reconfiguration interface.

The CSR register read/write needs to wait at least 2 clock cycles after csr_rst_n assertion.

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