Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

Download PDF
ID 683486
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP 2. Low Latency E-Tile 40G Ethernet IP Core Parameters 3. Getting Started 4. Functional Description 5. Reset 6. Interfaces and Signal Descriptions 7. Control, Status, and Statistics Register Descriptions 8. Debugging the Link 9. Ethernet Toolkit Overview 10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives 11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core 12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP x
1.1. Release Information 1.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Supported Features 1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support 1.4. Resource Utilization
1.3. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Family and Speed Grade Support x
1.3.1. Device Family Support 1.3.2. Low Latency E-Tile 40G Ethernet Intel® FPGA IP Device Speed Grade Support
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench 3.7. Compiling the Full Design and Programming the FPGA
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Ethernet Adaptation Flow 3.5.3. Placement Settings for the Low Latency E-Tile 40G Ethernet Core
3.6. Low Latency E-Tile 40G Ethernet IP Core Testbench x
3.6.1. Understanding the Testbench Behavior
4. Functional Description x
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description 4.2. User Interface to Ethernet Transmission
4.1. Low Latency E-Tile 40G Ethernet Core Functional Description x
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath 4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath 4.1.3. Link Fault Signaling Interface 4.1.4. Flow Control
4.1.1. Low Latency E-Tile 40G Ethernet Core TX MAC Datapath x
4.1.1.1. Frame Padding 4.1.1.2. Preamble Insertion 4.1.1.3. Inter-Packet Gap Generation and Insertion 4.1.1.4. Frame Check Sequence (CRC-32) Insertion
4.1.2. Low Latency E-Tile 40G Ethernet Core RX MAC Datapath x
4.1.2.1. IP Core Preamble Processing 4.1.2.2. IP Core Strict SFD Checking 4.1.2.3. Length/Type Field Processing 4.1.2.4. RX CRC Checking and Dynamic Forwarding
4.1.2.3. Length/Type Field Processing x
4.1.2.3.1. Length Checking
4.1.4. Flow Control x
4.1.4.1. TX Pause/PFC Flow Control Transmission 4.1.4.2. XON/XOFF Pause Frames
4.2. User Interface to Ethernet Transmission x
4.2.1. Order of Transmission 4.2.2. Bit Order For TX and RX Datapaths
6. Interfaces and Signal Descriptions x
6.1. TX MAC Interface to User Logic 6.2. RX MAC Interface to User Logic 6.3. Transceivers Signals 6.4. Transceiver Reconfiguration Signals 6.5. Avalon® Memory-Mapped Management Interface 6.6. Miscellaneous Status and Debug Signals 6.7. Reset Signals 6.8. Clocks 6.9. Flow Control Interface
7. Control, Status, and Statistics Register Descriptions x
7.1. PHY Registers 7.2. TX MAC Registers 7.3. RX MAC Registers 7.4. Pause/PFC Flow Control Registers
9. Ethernet Toolkit Overview x
9.1. Features
1. About the Low Latency E-Tile 40G Ethernet Intel® FPGA IP
2. Low Latency E-Tile 40G Ethernet IP Core Parameters
3. Getting Started
4. Functional Description
5. Reset
6. Interfaces and Signal Descriptions
7. Control, Status, and Statistics Register Descriptions
8. Debugging the Link
9. Ethernet Toolkit Overview
10. Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide Archives
11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core
12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

6.8. Clocks

You must set the transceiver reference clock (clk_ref) frequency to a value that the IP core supports. The Low Latency E-Tile 40G Ethernet IP core supports a clk_ref frequency of 156.25 MHz ±100 ppm. The ±100ppm value is required for any clock source providing the transceiver reference clock.

SyncE IP core variations are IP core variations for which you turn on Enable SyncE in the parameter editor. These variations provide the RX recovered clock as a top-level output signal.

The Synchronous Ethernet standard, described in the ITU-T G.8261, G.8262, and G.8264 recommendations, requires that the TX clock be filtered to maintain synchronization with the RX reference clock through a sequence of nodes. The expected usage is that user logic drives the TX PLL reference clock with a filtered version of the RX recovered clock signal, to ensure the receive and transmit functions remain synchronized. In this usage model, a design component outside the Low Latency E-Tile 40G Ethernet IP core performs the filtering.

Table 20.  Clock InputsDescribes the input clocks that you must provide.

Signal Name

Description

clk_ref

The input clock clk_ref is the reference clock for the transceiver RX CDR PLL.

This clock must have a frequency of 156.25 MHz with a ±100 ppm accuracy per the IEEE 802.3ba-2010 Ethernet Standard.

In addition, clk_ref must meet the jitter specification of the IEEE 802.3ba-2010 Ethernet Standard.

The PLL and clock generation logic use this reference clock to derive the transceiver and PCS clocks. The input clock should be a high quality signal on the appropriate dedicated clock pin. Refer to the relevant device datasheet for transceiver reference clock phase noise specifications.

clk_status

Clocks the control and status interface. The clock quality and pin chosen are not critical. clk_status is expected to be a 100–161 MHz clock.

reconfig_clk

Clocks the transceiver reconfiguration interface. The clock quality and pin chosen are not critical. reconfig_clk is expected to be a 100–161 MHz clock.

Table 21.  Clock OutputsDescribes the output clocks that the IP core provides. In most cases these clocks participate in internal clocking of the IP core as well.

Signal Name

Description

clk_txmac

The TX clock for the IP core is clk_txmac. The TX MAC clock frequency is 312.5  MHz.

clk_rxmac

The RX clock for the IP core is clk_rxmac. The RX MAC clock frequency is 312.5 MHz.

This clock is only reliable when rx_pcs_ready has the value of 1. The IP core generates clk_rxmac from a recovered clock that relies on the presence of incoming RX data.

clk_rx_recover RX recovered clock. This clock is available only if you turn on Enable SyncE in the Low Latency E-Tile 40G Ethernet parameter editor.

The RX recovered clock frequency is 156.25 MHz during normal operation.

Level Two Title