Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

2. Low Latency E-Tile 40G Ethernet IP Core Parameters

The Low Latency E-Tile 40G Ethernet parameter editor has an IP tab and the Main tab.

The Low Latency E-Tile 40G Ethernet parameter editor also includes an Example Design tab. For information about that tab, refer to the Low Latency E-Tile 40G Ethernet Design Example User Guide .

Table 8.   Low Latency E-Tile 40G Ethernet IP Core Parameters: Main Tab
Parameter Range Default Setting Description
General
Target transceiver tile

E-Tile

The tile type of the Intel® Quartus® Prime project specific target device. Specifies the transceiver tile on your target device. The Device setting of the Intel® Quartus® Prime project in which you generate the IP core determines the transceiver tile type.
Protocol speed 40GbE 40GbE Selects the Ethernet data rate.
Ready latency 0, 3 0 Selects the readyLatency value on the TX client interface. readyLatency is an Avalon® streaming interface property that defines the number of clock cycles of delay from when the IP core asserts the l2_tx_ready signal to the clock cycle in which the IP core can accept data on the TX client interface. Refer to the Avalon Interface Specifications.

Selecting a latency of 3 eases timing closure at the expense of increased latency for the TX datapath.

PCS/PMA Options
Enable SyncE Enabled, Disabled Disabled Exposes the RX recovered clock as an output signal. This feature supports the Synchronous Ethernet standard described in the International Telecommunication Union (ITU) Telecommunication Standardization Sector (ITU-T) G.8261, G.8262, and G.8264 recommendations.
PHY reference frequency

156.25 MHz

156.25 MHz

Sets the expected incoming PHY clk_ref reference frequency. The input clock frequency must match the frequency you specify for this parameter (±100ppm).
MAC Options
Enable TX CRC insertion Enabled, Disabled Enabled When enabled, TX MAC computes and inserts the CRC-32 checksum in the out-going Ethernet frame. When disabled, the TX MAC does not compute a 32-bit FCS in the TX MAC frame. Instead, the client must provide frames with at least 64 bytes, plus the Frame Check Sequence (FCS).
Enable link fault generation Enabled, Disabled Disabled When enabled, the IP core implements link fault signaling as defined in the IEEE 802.3-2012 IEEE Ethernet Standard. The MAC includes a Reconciliation Sublayer (RS) to manage local and remote faults. When enabled, the local RS TX logic can transmit remote fault sequences in case of a local fault and can transmit IDLE control words in case of a remote fault.
Enable preamble passthrough Enabled, Disabled Disabled When enabled, the IP core is in RX and TX preamble pass-through mode. In RX preamble pass-through mode, the IP core passes the preamble and Start Frame Delimiter (SFD) to the client instead of stripping them out of the Ethernet packet. In TX preamble pass-through mode, the client specifies the preamble and provides the SFD to be sent in the Ethernet frame.
Enable MAC stats counters Enabled, Disabled Enabled When enabled, the IP core includes statistics counters that characterize TX and RX traffic. The statistics module also supports shadow requests that verify counts by taking snapshots of intermediate results.
Enable Strict SFD check Enabled, Disabled Disabled When enabled, the IP core can implement strict SFD checking, depending on register settings.
Flow Control Options
Enable MAC flow control Enabled, Disabled Disabled When enabled, the IP core implements flow control. When either link partner experiences congestion, the respective transmit control sends pause frames.
Number of queues in priority flow control 1-8 8 Specifies the number of queues used in managing flow control.
Configuration, Debug and Extension Options
Enable Native PHY Debug Master Endpoint (NPDME) Enabled, Disabled Disabled

If this parameter is turned on, the E-Tile Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint that connects internally to the Avalon® memory-mapped slave interface for dynamic reconfiguration. The Native PHY Debug Master Endpoint can access the transceiver's reconfiguration space. It can perform certain tests and debug functions via JTAG using the System Console.

Enable JTAG to Avalon Master Bridge Enabled, Disabled Disabled

If turned on, the IP core includes a JTAG to Avalon® memory-mapped interface master bridge connecting internally to status and reconfiguration registers.

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