Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

4.1.1.4. Frame Check Sequence (CRC-32) Insertion

The TX MAC computes and inserts a CRC32 checksum in the transmitted MAC frame. The frame check sequence (FCS) field contains a 32-bit CRC value. The MAC computes the CRC32 over the frame bytes that include the source address, destination address, length, data, and pad (if applicable). The CRC checksum computation excludes the preamble, SFD, and FCS. The encoding is defined by the following generating polynomial:

FCS(X) = X32 +X26 +X23 +X22 +X16 +X12 +X11 +X10 +X8 +X7 +X5 +X4 +X2 +X1 +1

CRC bits are transmitted with MSB (X32) first.

You can configure your IP core TX MAC to implement TX CRC insertion or not, by turning Enable TX CRC insertion on or off in the IP core parameter editor. By default, the CRC insertion feature is enabled.

In CRC pass-through mode, the l2_tx_endofpacket and l2_rx_endofpacket along with l2_tx_empty and l2_rx_empty point to the last byte of Frame Check Sequence (FCS).
Note: In TX CRC pass-through mode, you must provide frames with at least 64 bytes. If Flow control mode is enabled, the IP core generates and inserts the CRC for flow control packets.
If you have not selected the CRC pass-through mode, the l2_tx_endofpacket and l2_rx_endofpacket along with l2_tx_empty and l2_rx_empty point to the last byte before the first FCS.
Note: The TX CRC insertion requires to set Flow control mode to 1.

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