Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

3.2. Specifying the Low Latency E-Tile 40G Ethernet IP Core Parameters and Options

The Low Latency E-Tile 40G Ethernet parameter editor allows you to quickly configure your custom IP variation. Use the following steps to specify IP core options and parameters in the Intel® Quartus® Prime Pro Edition software.
  1. In the Intel® Quartus® Prime Pro Edition, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device.
  2. In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. The New IP Variation window appears.
  3. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip> .ip.
  4. Click OK. The parameter editor appears.
  5. On the IP tab, specify the parameters for your IP core variation. Refer to Low Latency E-Tile 40G Ethernet IP Core Parameters for information about specific IP core parameters.
  6. Optionally, to generate a simulation testbench or compilation and hardware design example, follow the instructions in the Low Latency E-Tile 40G Ethernet Design Example User Guide .
  7. Click Generate HDL. The Generation dialog box appears.
  8. Specify output file generation options, and then click Generate. The IP variation files generate according to your specifications.
  9. Click Finish. The parameter editor adds the top-level .ip file to the current project automatically. If you are prompted to manually add the .ip file to the project, click Project > Add/Remove Files in Project to add the file.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

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