Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

7. Control, Status, and Statistics Register Descriptions

This section provides information about the memory-mapped registers. You access these registers using the IP core Avalon® memory-mapped control and status interface. The registers use 32-bit addresses; they are not byte addressable.

Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified result. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP core variation, or to register bits that are not defined in your IP core variation, have an unspecified result. You should consider these registers and register bits Reserved. Although you can only access registers in 32-bit read and write operations, you should not attempt to write or ascribe meaning to values in undefined register bits.

Table 23.  Register Base Addresses
Word Offset Register Type
0x300-0x3FF PHY registers
0x400-0x4FF TX MAC registers
0x500-0x5FF RX MAC registers
0x600-0x6FF TX Flow Control registers
0x700-0x7FF RX Flow Control registers
0x800-0x8FF Statistics Counter registers - TX direction
0x900-0x9FF Statistics Counter registers - RX direction

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