Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

3.5.1. Pin Assignments

When you integrate your Low Latency E-Tile 40G Ethernet core instance in your design, you must make appropriate pin assignments. While compiling the IP core alone, you can create virtual pins to avoid making specific pin assignments for top-level signals. When you are ready to map the design to hardware, you can change to the correct pin assignments.

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