Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

11. Comparison Between Low Latency E-Tile 40G Ethernet Core and Low Latency 40GbE IP Core

Table 29.  Comparison Between the Low Latency E-Tile 40G Ethernet Core and the Low Latency 40G Ethernet Intel® FPGA IP Core
The comparison is defined relative to these versions:
  • Low Latency E-Tile 40G Ethernet IP core available with the Intel® Quartus® Prime Pro Edition software release v20.1.
  • Low Latency 40G Ethernet Intel® FPGA IP core available with the Quartus Prime Pro 17.1 Stratix 10 ES Editions software.
This table does not list individual signal name and register differences.

Property

Low Latency E-Tile 40G Ethernet IP Core

Low Latency 40G Ethernet Intel FPGA IP Core

Transceiver tile support

E-tile L-tile, H-tile

Device support

Supports Intel® Stratix® 10 and Intel® Agilex™ device family.

Supports Intel® Stratix® 10 device family.

Reset

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Provides three asynchronous hard reset signals (general, receiver only, and transmitter only) and three soft reset register bits.

Client interface width

Avalon® streaming interface 128-bit data bus

Avalon® streaming interface 128-bit data bus

Avalon® streaming transmitter interface readyLatency Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter). Avalon® streaming transmitter interface readyLatency configurable at 0 or 3 (parameter).
Preamble passthrough Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP core provides the RX preamble on a separate bus, l2_rx_preamble[63:0]. Available as a configuration option (parameter). When preamble passthrough is turned on, you must provide the preamble on a separate bus, l2_tx_preamble[63:0], and the IP core provides the RX preamble on a separate bus, l2_rx_preamble[63:0].
Interface to transceiver TX PLL Not required. You must instantiate a single TX PLL IP core to connect to the single tx_serial_clk input pin of the Low Latency 40G Ethernet Intel® FPGA IP core.
Statistics counters Available as a configuration option (parameter). Available as a configuration option (parameter).
Statistics counter increment vectors l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled. l2_txstatus_data, l2_txstatus_error, and l2_rxstatus_data signals available on client interface, whether or not statistics registers are enabled.
40GBASE-KR4 Not supported. Available as a configuration option. Configurable support for 40GBASE-KR4 or 40GBASE-CR4. Implements the IEEE Backplane Ethernet Standard 802.3-2012.
Flow control Available as a configuration option (parameter). Available as a configuration option (parameter).
1588 PTP support Not supported. Not supported.
Enable alignment of EOP on FCS word Always turned on. Always turned on.
Minimum average interpacket gap Value is 12 bytes. Value is 12 bytes.

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