Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

3.7. Compiling the Full Design and Programming the FPGA

You can use the Start Compilation command on the Processing menu in the Intel® Quartus® Prime software to compile your design. After successfully compiling your design, program the targeted Intel® FPGA with the Programmer and verify the design in hardware.

Note: The Low Latency E-Tile 40G Ethernet core design example synthesis directories include Synopsys Constraint (.sdc) files that you can copy and modify for your own design.

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