Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

4.1. Low Latency E-Tile 40G Ethernet Core Functional Description

The Low Latency E-Tile 40G Ethernet core implements an Ethernet MAC in accordance with the IEEE 802.3 Ethernet Standard. The IP core implements an Ethernet PCS and PMA (PHY) that handles the frame encapsulation and flow of data between a client logic and Ethernet network.

Figure 4.  Low Latency E-Tile 40G Ethernet Core Block DiagramMain blocks, internal connections, and external block requirements.

In the TX direction, the MAC assembles packets and sends them to the PHY. It completes the following tasks:

  • Accepts client frames.
  • Inserts the inter-packet gap (IPG), preamble, start of frame delimiter (SFD), and padding. The source of the preamble and SFD depends on whether the IP core is in preamble-pass-through mode.
  • Adds the CRC bits if enabled.
  • Updates statistics counters if enabled.

In the RX direction, the PMA passes frames to the PCS that sends them to the MAC. The MAC completes the following tasks:

  • Performs CRC and malformed packet checks.
  • Updates statistics counters if enabled.
  • Strips out the CRC, preamble, and SFD.
  • Passes the remainder of the frame to the client.

In preamble pass-through mode, the MAC passes on the preamble and SFD to the client instead of stripping them out. In RX CRC pass-through mode, the MAC passes on the CRC bytes to the client and asserts the end-of-packet signal in the same clock cycle as the final CRC byte.

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