Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

6.6. Miscellaneous Status and Debug Signals

The miscellaneous status and debug signals are asynchronous.
Table 18.   Avalon® Memory-Mapped Interface

Signal

Direction

Description

tx_lanes_stable Output Asserted when all TX lanes are stable and ready to transmit data.
rx_block_lock Output Asserted when all lanes have identified 66-bit block boundaries in the serial data stream.
rx_am_lock Output Asserted when all lanes have identified alignment markers in the data stream.
rx_pcs_ready Output Asserted when the RX lanes are fully aligned and ready to receive data.
local_fault_status Output Asserted when the RX MAC detects a local fault. This signal is available only if you turn on Enable link fault generation in the parameter editor.
remote_fault_status Output Asserted when the RX MAC detects a remote fault. This signal is available only if you turn on Enable link fault generation in the parameter editor.

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