Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

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ID 683486
Date 8/31/2021
Public
Document Table of Contents

1. About the Low Latency E-Tile 40G Ethernet Intel FPGA IP

Updated for:
Intel® Quartus® Prime Design Suite 21.2
IP Version 21.0.0

The Low Latency E-Tile 40-Gbps Ethernet (LL E-Tile 40GbE) IP core is used in multiple variants of the Intel® Stratix® 10 and Intel® Agilex™ device families. The IP core implements the IEEE 802.3-2010 40G Ethernet Standard and includes options to support unidirectional transport as defined in Clause 66 of the IEEE 802.3-2012 Ethernet Standard.

The MAC client side interface for the Low Latency E-Tile 40G Ethernet IP core is a 128-bit Avalon® streaming interface and a 32-bit Avalon® memory-mapped interface control path. The network interfaces are standard XLAUI interfaces.

The IP core provides standard media access control (MAC), physical coding sublayer (PCS), and physical medium attachment (PMA) functions.

Figure 1.  Low Latency E-Tile 40G Ethernet Block DiagramMain blocks, internal connections, and external block requirements.

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