Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

6.3. Transceivers Signals

Table 15.   Transceiver Signals

Signal

Direction

Description

tx_serial[3:0] Output TX transceiver data. Each tx_serial bit becomes two physical pins that form a differential pair.
rx_serial[3:0] Input RX transceiver data. Each rx_serial bit becomes two physical pins that form a differential pair.
clk_ref Input The PLL reference clock. Input to the clock data recovery (CDR) circuitry in the RX PMA. The frequency of this clock is 156.25 MHz.

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