Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

7.1. PHY Registers

Table 24.  PHY RegistersThe global hard reset csr_rst_n resets all of these registers. The TX reset tx_rst_n and RX reset rx_rst_n signals do not reset these registers.
Addr Name Description Reset Access
0x300 REVID IP core PHY module revision ID.

0x0627 2016

RO
0x301 SCRATCH Scratch register available for testing. 0x0000 0000 RW
0x302 PHY_NAME_0 First characters of IP core variation identifier string, "0040" . The "00" is unprintable.

0x0000 3430

RO
0x303 PHY_NAME_1 Next characters of IP core variation identifier string, "00GE". The "00" is unprintable. 0x0000 4745 RO
0x304 PHY_NAME_2 Final characters of IP core variation identifier string, "0pcs". The "0" is unprintable. 0x0070 6373 RO
0x310 PHY_CONFIG PHY configuration registers. The following bit fields are defined:
  • Bit[0]: : sys_rst . Full system reset (except registers). Set this bit to initiate the internal reset sequence.
  • Bit[1]: soft_txp_rst. TX soft reset. Resets TX PCS and TX MAC.
  • Bit[2]: soft_rxp_rst. RX soft reset. Resets RX PCS and RX MAC.
  • Bits[31:3]: Reserved.

29'hX_3'b0 4

RW
0x312 WORD_LOCK When asserted, indicates that the virtual channel has identified 66 bit block boundaries in the serial data stream.

28'hX4'b0 4

RO
0x314 EIO_FLAG_SEL Supports indirect addressing of individual FIFO flags in the PCS Native PHY IP core. Program this register with the encoding for a specific FIFO flag. The flag values (one per transceiver) are then accessible in the EIO_FLAGS register.

The value in the EIO_FLAG_SEL register directs the IP core to make available the following FIFO flag:

  • 3'b000: TX FIFO full
  • 3'b001: TX FIFO empty
  • 3b010: TX FIFO partially full
  • 3'b011: TX FIFO partially empty
  • 3b100: RX FIFO full
  • 3b101: RX FIFO empty
  • 3b110: RX FIFO partially full
  • 3b111: RX FIFO partially empty
29'hX3'b0 4 RW
0x315 EIO_FLAGS PCS indirect data. To read a FIFO flag, set the value in the EIO_FLAG_SEL register to indicate the flag you want to read. After you specify the flag in the EIO_FLAG_SEL register, each bit [n] in the EIO_FLAGS register has the value of that FIFO flag for the transceiver channel for lane [n].

28'hX4'b0 4

RO
0x321 EIO_FREQ_LOCK Each asserted bit indicates that the corresponding lane RX clock data recovery (CDR) phase-locked loop (PLL) is locked.

28'hX4'b0 4

RO
0x322 PHY_CLK The following encodings are defined:
  • Bit[0]: Indicates if the TX PCS is ready
29'hX3'b00 4 RO
0x323 FRM_ERR

Each asserted bit indicates that the corresponding virtual lane has a frame error. You can read this register to determine if the IP core sustains a low number of frame errors, below the threshold to lose word lock. These bits are sticky, unless the IP core loses word lock. Write 1'b1 to the SCLR_FRM_ERR register to clear.

If the IP core loses word lock, it clears this register.

28'hX_4'b0 4

RO
0x324 SCLR_FRM_ERR Synchronous clear for FRM_ERR register. Write 1'b1 to this register to clear the FRM_ERR register and bit [1] of the LANE_DESKEWED register. A single bit clears all sticky framing errors.

This bit does not auto-clear. Write a 1'b0 to continue logging frame errors.

0x0 RW
0x325 EIO_RX_SOFT_PURGE_S

Set bit [0] to clear the RX FIFO for both physical lanes.

0x0000

RW

0x326 RX_PCS_FULLY_ALIGNED_S Indicates the RX PCS is fully aligned and ready to accept traffic.
  • Bit[0]: RX PCS fully aligned status.

31'hX1'b0 4

RO
0x329 LANE_DESKEWED
The following encodings are defined:
  • Bit [0]: Indicates all lanes are deskewed.
  • Bit [1]: When asserted indicates a change in lanes deskewed status. To clear this sticky bit, write 1'b1 to the corresponding bit of the SCLR_FRM_ERR register. This is a latched signal.
30'hX2'b00 4 RO
0x331 PHY_RX_DELAY Test and debug feature to test deskew. Allows you to insert a programmable skew on one physical channel.
  • Bit[0]: Allows you to you to shift 33 bits for incoming stream in physical channel 0, effectively inserting sew on two of the virtual lanes.
  • Bit[5:1]: Allows you to insert a 1-32 word delay on the two virtual channels arriving on physical lane 0. To use bits[5;1], you must set an RX PCS dynamic parameter that is not exposed at the top level (DYNAMIC_SKEW).
26'hX_6'b0 RW
0x341 KHZ_RX The register indicates the value of RX clock (clk_rxmac) frequency. Apply the following definition for the frequency value:

[(Register value 5 * clk_status)/10] KHZ

0x0000 0000 RO
0x342 KHZ_TX The register indicates the value of TX clock (clk_txmac) frequency. Apply the following definition for the frequency value:

[(Register value 5 * clk_status)/10] KHZ

0x0000 0000 RO
4 X means "Don't Care".
5 Register value convert in decimal.

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