Low Latency E-Tile 40G Ethernet Intel® FPGA IP User Guide

ID 683486
Date 8/31/2021
Public
Document Table of Contents

12. Document Revision History for Low Latency E-Tile 40G Ethernet Intel FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.08.31 21.2 21.0.0 Corrected typo in section: Ethernet Adaptation Flow.
2021.06.21 21.2 21.0.0
  • Removed support for NCSim simulator.
  • Removed errorneous description from section: Transceivers Signals.
2020.10.05 20.3 21.0.0
  • Corrected the width of the reconfiguration address from reconfig_address[21:0] to reconfig_address[20:0].
  • Revised the Flow Control Signals table to update the following signal description:
    • pause_insert_tx0[(FCQN-1):0]
    • pause_insert_tx1[(FCQN-1):0]
    • pause_insert_rx[(FCQN-1):0]
  • Added new section: Ethernet Toolkit Overview.
2020.06.22 20.2 20.0.0
  • Added support for the Intel® Agilex™ device family.
  • Removed VCCR_GXB and VCCT_GXB supply voltage for the transceiver parameter from the Low Latency E-Tile 40G Ethernet IP Core Parameters: Main Tab section. This parameter is not utilized in the Low Latency E-Tile 40G Ethernet Intel® FPGA IP.
  • Updated reconfig_address[21:0] description in the Transceiver Reconfiguration Signals section.
2020.04.20 20.1 19.1.0 Initial release.

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