DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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5.8.3. Video Interface

The core sends video to be encoded through the txN_video_in or txN_video_in_im interface, depending on whether or not you turn on the TX Video IM Enable parameter.

Table 30.  Video Input Feature ComparisonsThe table below shows the simplified comparison between the 2 different ways to feed video data to the source core.
Interface Video Data Constraints Calculated MSA Parameters User-provided Required MSA Parameters User-provided Optional MSA Parameters Adaptive Sync Support

txN_video_in

  • HS/VS/DE and real pixel clock available
  • Video data temporally correct
All None None No

txN_video_in_im

Video data temporally correct

  • MVID
  • HWIDTH
  • VHEIGHT
HTOTAL
  • VTOTAL
  • HSP
  • HSW
  • HSTART
  • VSTART
  • VSP
  • VSW
Yes