DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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Document Table of Contents

6.6. Sink Interfaces

The following tables summarize the sink’s interfaces. Your instantiation contains only the interfaces that you have enabled.

Table 42.  Controller Interface

Interface

Port Type

Clock Domain

Port

Direction

Description

clk

Clock

N/A

clk

Input

Clock for embedded controller.

reset

Reset

clk reset

Input

Active-high reset signal for embedded controller.

rx_mgmt

AV-MM

clk rx_mgmt_address[8:0]

Input

32-bit word addressing address.

rx_mgmt_chipselect

Input

Must be asserted for valid read or write access.

rx_mgmt_read

Input

Must be asserted to indicate a read transfer.

rx_mgmt_write

Input

Must be asserted to indicate a write transfer.

rx_mgmt_writedata[31:0]

Input

Data for write transfers.

rx_mgmt_readdata[31:0]

Output

Data for read transfers.

rx_mgmt_waitrequest

Output

Asserted when the DisplayPort Intel® FPGA IP is unable to respond to a read or write request. Forces the GPU to wait until the IP is ready to proceed with the transfer.

rx_mgmt_irq

IRQ

clk

rx_mgmt_irq

Output

The IP asserts this signal to issue an interrupt to the GPU.

Controller Interface

Table 43.  Transceiver Management Interface n is the number of RX lanes.

Interface

Port Type

Clock Domain

Port

Direction

Description

xcvr_mgmt_clk

Clock

N/A

xcvr_mgmt_clk

Input

Transceiver management clock.

clk_cal

Clock

N/A

clk_cal Input

Calibration clock.

rx_reconfig

Conduit

xcvr_mgmt_clk rx_link_rate_8bits[7:0]

Output

Transceiver link rate reconfiguration handshaking.

rx_reconfig_req

Output

rx_reconfig_ack

Input

rx_reconfig_busy

Input

rx_analog_reconfig

Conduit

xcvr_mgmt_clk rx_vod [2n-1:0]

Output

Transceiver analog reconfiguration handshaking.

rx_emp [2n-1:0]

Output

rx_analog_reconfig_req

Output

Note: Value of rx_link_rate 8bits[7:0]: 0x06 = 1.62 Gbps, 0x0a = 2.70 Gbps, 0x14 = 5.40 Gbps, 0x1e = 8.10 Gbps, 0x01 = 10 Gbps
Note: rx_link_rate[1:0] is depreciated.

Transceiver Reconfiguration Interface

Table 44.  Video Interface v is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad), and N is the stream number.

Interface

Port Type

Clock Domain

Port

Direction

Description

rxN_vid_clk

Clock

N/A

rxN_vid_clk

Input

Video clock.

rxN_video_out

Conduit

rx_vid_clk rxN_vid_valid[p-1:0]

Output

Each bit is asserted when all other signals (except rxN_vid_overflow) on this port are valid and the corresponding pixel belongs to active video.

Width configurable.

rxN_vid_sol

Output

Start of video line.

rxN_vid_eol

Output

End of video line.

rxN_vid_sof

Output

Start of video frame.

rxN_vid_eof

Output

End of video frame.

rxN_vid_locked

Output

1 = Video locked

0 = Video unlocked

rxN_vid_overflow

Output

1 = Video data overflow detected

0 = No overflow detected

This signal is always valid.

rxN_vid_interlace

Output

1 = Interlaced

0 = Progressive

rxN_vid_field

Output

1 = Top field

0 = Bottom field (or progressive)

rxN_vid_data[3v*p-1:0]

Output

Width configurable.

Video Interface

Table 45.  Video Interface (RX AXI4-stream Video Interface)v is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad).
Interface Port Type Clock Domain Port Direction Description
rx_axi4s_clk Clock N/A rx_axi4s_clk Input AXI4-stream video clock (300Mhz)
rx_axi4s_reset Reset rx_axi4s_clk rx_axi4s_reset Input AXI4-stream video reset
rx_axi4s_vid_in Conduit rx_axi4s_vid_in_tdata[(3v+7/8)*p*8-1:0] Output AXI4-stream video data
rx_axi4s_vid_in_tuser[(3v+7/8)*p-1:0] Output AXI4-stream video data start of frame
rx_axi4s_vid_in_tvalid Output AXI4-stream video data valid
rx_axi4s_vid_in_tready Input AXI4-stream video data ready
rx_axi4s_vid_in_tlast Output AXI4-stream video data end of line
Table 46.  AUX Interface

Interface

Port Type

Clock Domain

Port

Direction

Description

aux_clk

Clock

N/A

aux_clk

Input

AUX channel clock.

aux_reset

Reset

aux_clk aux_reset

Input

Active-high AUX channel reset.

rx_aux

Conduit

aux_clk rx_aux_in

Input

AUX channel data input.

rx_aux_out

Output

AUX channel data output.

rx_aux_oe

Output

Output buffer enable.

rx_hpd

Output

Hot plug detect.

rx_cable_detect

Input

Upstream cable detect.

rx_pwr_detect

Input

Upstream power detect.

rx_aux_debug

AV-ST

aux_clk rx_aux_debug_data[31:0]

Output

Formatted AUX channel debug data.
rx_aux_debug_valid

Output

Asserted when all the other signals on this port are valid.

rx_aux_debug_sop

Output

Start of packet (start of AUX request or reply).

rx_aux_debug_eop

Output

End of packet (end of AUX request or reply).

rx_aux_debug_err

Output

Indicates if the IP detects an error in the current byte.

rx_aux_debug_cha

Output

The channel number for data being transferred on the current cycle. Used as AUX channel data direction.

1 = Reply (to DisplayPort source)

0 = Request (from DisplayPort source)

EDID

(rx_edid)

AV-MM aux_clk rx_edid_address[7:0]

Output

8-bit byte addressing address.
rx_edid_read

Output

Asserted to indicate a read transfer.

rx_edid_write

Output

Asserted to indicate a write transfer.

rx_edid_writedata[7:0]

Output

Data for write transfers.

rx_edid_readdata[7:0]

Input

Data for read transfers.

rx_edid_waitrequest

Input

Must be asserted when the Slave is unable to respond to a read or write request. Forces the DisplayPort Intel® FPGA IP to wait until the Slave is ready to proceed with the transfer.

AUX Interface

Table 47.  Debugging Interface s is the number of symbols per clock and N is the stream number.

Interface

Signal Type

Clock Domain

Port

Direction

Description

Link Parameters (rx_params)

Conduit

aux_clk rx_lane_count[4:0]

Output

Sink current link lane count value.

Debugging (rxN_stream)

Conduit

rx_ss_clk rxN_stream_data[4*8*s–1:0]

Output

Post scrambler data.

rxN_stream_ctrl[4*s–1:0]

Output

Post scrambler comma marker. The IP asserts each bit when the relative 8-bit byte is a comma code, and deasserts each bit when the byte is a data value.

Bit 0 qualifies rxN_stream_data[7:0] byte, bit 1qualifies the rxN_stream_data[15:8] byte, and so on.

rxN_stream_valid

Output

Asserted for one clock cycle when rxN_stream_data[63:0] and rxN_stream_ctrl[7:0] are valid.

rxN_stream_clk

Output

Port clock.

Debugging Interface

Table 48.  Secondary Interface N is the stream number; for example, rx_msa_conduit represents Stream 0, rx1_msa_conduit represents Stream 1, and so on .

Interface

Signal Type

Clock Domain

Port

Direction

Description

rx_ss_clk

Clock

N/A

rx_ss_clk

Output

Clock.

MSA (rxN_msa_conduit)

Conduit

rx_ss_clk rxN_msa[216:0]

Output

Output for current MSA parameters received from the source.

Secondary Stream (rxN_ss)

AV-ST

rx_ss_clk

rxN_ss_data[159:0]

Output

Secondary stream interface.

rxN_ss_valid

Output

rxN_ss_sop

Output

rxN_ss_eop

Output

Secondary Stream Interface

Table 49.  Audio Interface m is the number of RX audio channels. N is the stream number; for example, rx_audio represents Stream 0, rx1_audio represents Stream 1, and so on .

Interface

Signal Type

Clock Domain

Port

Direction

Description

Audio

(rxN_audio)

Conduit rx_ss_clk rxN_audio_lpcm_data[m*32–1:0]

Output

N channels of 32-bit audio sample data.
rxN_audio_valid

Output

Asserted when valid data is available on rxN_audio_lpcm_data.

rxN_audio_mute

Output

Asserted when audio is muted.

rxN_audio_infoframe[39:0]

Output

40-bit bundle containing the Audio InfoFrame packet.

Audio Interface

Table 50.  RX Transceiver Interface n is the number of RX lanes, s is the number of DisplayPort 1.4 symbols per clock. For any link rates equal to or below UHBR10, w = n * s * 10. For link rates above UHBR10, w = 64.
Note: Connect the DisplayPort signals to the Native PHY signals of the same name.

Interface

Port Type

Clock Domain

Port

Direction

Description

RX transceiver interface Clock

N/A

rx_std_clkout

Input

RX transceiver recovered clock.

Equivalent to Link Speed Clock (ls_clk).

All lanes on this interface use a single clock, sourced from DisplayPort Lane 0.

Conduit rx_xcvr_clkout rx_parallel_data[w–1:0]

Input

Parallel data from RX transceiver.

Conduit rx_xcvr_clkout rx_restart

Output

Use to reset the RX PHY Reset Controller when the RX data loses alignment.

Note: Required for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices. Not used in Arria V, Cyclone V, and Stratix V devices.
Conduit

N/A

rx_is_lockedtoref[n–1:0]

Input

When asserted, indicates that the RX CDR PLL is locked to the reference clock.

Conduit

N/A

rx_is_lockedtodata[n–1:0]

Input

When asserted, indicates that the RX CDR PLL is locked to the incoming data.

Conduit rx_xcvr_clkout rx_bitslip[n–1:0]

Output

Use to control bit slipping manually.

Conduit

N/A

rx_cal_busy[n–1:0]

Input

Calibration in progress signal from RX transceiver.

Conduit xcvr_mgmt_clk rx_analogreset[n–1:0]

Output

When asserted, resets the RX CDR.

Note: Required only for Arria V, Cyclone V, and Stratix V devices.
Conduit xcvr_mgmt_clk rx_digitalreset[n–1:0]

Output

When asserted, resets the RX PCS.

Note: Required only for Arria V, Cyclone V, and Stratix V devices.
Conduit xcvr_mgmt_clk rx_set_locktoref[n–1:0]

Output

Forces the RX CDR circuitry to lock to the phase and frequency of the input reference clock.

Conduit xcvr_mgmt_clk rx_set_locktodata[n–1:0]

Output

Forces the RX CDR circuitry to lock to the received data.

RX Transceiver Interface

Table 51.  HDCP InterfaceApplicable only when you turn on the Support HDCP 2.3 or Support HDCP 1.3 parameters.

Interface

Port Type

Clock Domain

Port

Direction

Description

HDCP Clocks (hdcp_clks) Reset hdcp_reset Input Main asynchronous reset for HDCP.
Clock crypto_clk Input

HDCP 2.3 clock for authentication and cryptographic layer.

You can use any clock with a frequency up to 200 MHz.

Not applicable for HDCP 1.3.

Note: The clock frequency determines the authentication latency.
rpt_msg_clk Input HDCP clock for the Repeater registers in the Control and Status Register layer.

Typically, shares the clock (100 MHz) that drives the repeater downstream Nios® II processor.

Repeater Message Interface (rx_rpt_msg) Avalon-MM rpt_msg_clk rx_rpt_msg_addr[7:0] Input

The Avalon memory-mapped slave port that provides access to the Repeater registers, mainly for ReceiverID_List and RxInfo. This interface is expected to operate at repeater downstream Nios II processor clock domain.

Because of the extremely large bit portion of message, the IP transfers the message in burst mode with full handshaking mechanism. Write transfers always have a wait time of 0 cycle while read transfers have a wait time of 1 cycle.

The addressing should be accessed as word addressing in the Platform Designer flow. For example, addressing of 4 in the Nios II software selects the address of 1 in the slave.

rx_rpt_msg_wr Input
rx_rpt_msg_rd Input
rx_rpt_msg_wrdata[31:0] Input
rx_rpt_msg_rddata[31:0] Output
HDCP Key and Status Interface (rx_hdcp) Conduit (Key) crypto_clk

rx_kmem_wait[0] (HDCP 2.3)

rx_kmem_addr[1] (HDCP 1.3)

Input

Always keep this signal asserted until the key is ready to be read.

This signal is not available if you turn on the Support HDCP Key Management parameter.

rx_kmem_rdaddr[7:0] (HDCP 2.3)

rx_kmem_rdaddr[13:8] (HDCP 1.3)

Output Key read address bus.

This signal is not available if you turn on the Support HDCP Key Management parameter.

rx_kmem_q[31:0] (HDCP 2.3)

rx_kmem_q[87:32] (HDCP 1.3)

Input Key read data transfer.

Read transfer always have 1 cycle of wait time.

This signal is not available if you turn on the Support HDCP Key Management parameter.

Avalon-MM clk rx_hdcp1_kmem_wr Input

The Avalon® memory-mapped slave port provides write access to internal HDCP 1.3 key storage.

Write transfers always have a wait time of 0.

The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow.

For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave.

These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 1.3 parameter.

rx_hdcp1_kmem_wrdata[31:0] Input
rx_hdcp1_kmem_addr[6:0] Input
Avalon-MM hdcp_i2c_clk rx_hdcp2_kmem_wr Input

The Avalon® memory-mapped slave port provides write access to internal HDCP 2.3 key storage.

Write transfers always have a wait time of 0.

The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow.

For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave.

These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 2.3 parameter.

rx_hdcp2_kmem_wrdata[31:0] Input
rx_hdcp2_kmem_addr[7:0] Input
Conduit rx_std_clkout[0] rx_hdcp1_enabled Output This signal is asserted by the IP if the incoming video and auxiliary data are HDCP 1.3 encrypted.
rx_hdcp2_enabled Output This signal is asserted by the IP if the incoming video and auxiliary data are HDCP 2.3 encrypted.
rx_streamid_type Output
  • 0: The received stream type is 0.
  • 1: The received stream type is 1.
clk rx_hdcp1_disable Input Assert this signal to disable the HDCP 1.3 IP.
Note: You must reset the HDCP IP (hdcp_reset) and trigger a Hot Plug event after toggling this signal.
rx_hdcp2_disable Input Assert this signal to disable the HDCP 2.3 IP.
Note: You must reset the HDCP IP (hdcp_reset) and trigger a Hot Plug event after toggling this signal.