DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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11.1.5. DPRX_BER_CNT1

These registers are exposed in DPCD locations SYMBOL_ERROR_COUNT_LANE2 and SYMBOL_ERROR_COUNT_LANE3.

Address: 0x0004

Direction: RO

Reset: 0x00000000

Table 160.  DPRX_RX_STATUS Bits

Bit

Bit Name

Function

31

Unused

30:16

CNT3 Symbol error counter for lane 3

15

Unused

14:0

CNT2 Symbol error counter for lane 2