DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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4.3.6. DisplayPort Post Link Training Adjust Request Flow (LQA)

After Link Training completes, you can use the Post Link Training Adjust Request Sequence to fine-tune the transmitter driver setting and receiver equalization setting.

The DisplayPort sink supports Post Link Training Adjust Request Sequence feature (as defined in the VESA DisplayPort Standard 1.3).

The DisplayPort Intel® FPGA IP controls this feature.
  1. During Link Training Sequence, when the source reads DPCD offset 0x00002, and the sink have 0x00002 bit [5] (POST_LT_ADJ_REQ_SUPPORT) set to 1.
  2. If the source supports this feature, it writes to offset 0x00101 bit [5] (POST_LT_ADJ_REQ_GRANTED) to grant Post Link Training Adjust Request.
  3. After Link Training Sequence completes, the source writes to offset 0x00102 to disable Link Training.
  4. The sink sets DPCD 0x00204 bit [1] (POST_LT_ADJ_REQ_IN_PROGRESS) to 1 and fine-tunes the Link driver setting (Voltage swing and Pre-emphasis).
  5. The source reads offset 0x00204 bit [1] to check if Sink Post Link Training Adjust Sequence is in progress.
  6. After 5 – 10 ms, the source reads DPCD ADJUST_REQUEST_LANE x (0x00206 – 0x00207).
    • If the value changes, the source writes to offset 0x00206 – 0x00207 to configure the Link driver setting accordingly to the requested value.
    • If value not changed, repeat steps 5 – 6. If these steps are repeated 6 times, the source clears offset 0x00101 bit [5] to not grant and proceed to Normal Active Video Transmission.
  7. If the sink device's Link Status (0x00202 – 0x00204) clears after step 6,
    • Abort Post Link Training Adjust Request Sequence.
    • The source clears offset 0x00101 bit [5] (not grant).
    • Restart with Link Training Sequence 1.
Note:

All the POST_LT_ADJ_REQ registers and flow definition are available only in the VESA DisplayPort Standard 1.3 .