DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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Document Table of Contents

11.4.1. DPRX_FEC_CONFIG

FEC Configuration Register

Address: 0x0009

Direction: RW

Reset: 0x00000000

Table 164.  DPTX_FEC_CONFIG Bits

Bit

Bit Name

Function

31:7

Unused

6

PRECODING_DISABLE
  • 0 = Pre-coding is enabled (default)
  • 1 = Pre-coding is disabled
5 AGGREGATED_ENABLED_LANES_ERRORS
  • 0 = Not enabled
  • 1 = Enabled (reported value is aggregated across all enabled lanes)
4:3 FEC_LANE_DEC_SEL
  • 00 = Lane/Decoder 0
  • 01 = Lane/Decoder 1
  • 10 = Lane/Decoder 2
  • 11 = Lane/Decoder 3
2:0 FEC_ERR_COUNT_SEL
  • 000 = FEC_ERROR_COUNT_DIS
  • 001 = UNCORRECTED_BLOCK_ERROR_COUNT
  • 010 = CORRECTED_BLOCK_ERROR_COUNT
  • 011 = CORRECTED_BIT_ERROR_COUNT
  • 100 = PARITY_BLOCK_ERROR_COUNT
  • 101 = PARITY_BIT_ERROR_COUNT
Note: (100) Parity Block Error Count and (101) Parity Bit Error Count are no longer used in 128b/132b Channel Coding per DisplayPort v2.0 Errata E11. Both these counters are expected to stay zero when in 128b/132b.