DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

10.10.2.2. VIDEO_MODE_MATCH (0X51)

Table 135.  VIDEO_MODE_MATCH (0x51)
Name Bit(s) Access Description Reset
Video mode match 31:0 RO Before any user specified mode is matched, this register reads back 0 indicating the default values are selected. Once a match has been made,the register reads back 0x1. 0x0