DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

10.3.14. DPTX_TEST_264BIT_PATTERN9

Address: 0x001D

Direction: RW

Reset: 0x00000000

Table 94.  DPTX_TEST_264BIT_PATTERN9 Bits

Bit

Bit Name

Function

31:8

Reserved

7:0

264BIT_PATTERN9

Bits 263:256 of the 264 bit custom pattern for PHY compliance test.