DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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5. DisplayPort Source

The DisplayPort source consists of a DisplayPort encoder block, a transceiver management block, a controller interface block, and an HDCP interface block with an Avalon® memory-mapped interface for connecting with an embedded controller such as a Nios® II processor.

Figure 12. DisplayPort Source Top-Level Block Diagram
  
Figure 13. DisplayPort 1.4 Source Functional Block Diagram

The source accepts a standard H-sync, V-sync, and data enable video stream for encoding. The IP latches and processes the video data, such as color reordering, before processing it using the txN_video_in input. N represents the stream number: tx_video_in (Stream 0), tx1_video_in (Stream 1), tx2_video_in (Stream 2), and tx3_video_in (Stream 3). Streams 1, 2, and 3 are only available when you turn on the Support MST parameter and specify the Max stream count parameter to 2, 3, or 4 streams respectively.

The video data width supports 6 to 16 bits per color (bpc) and is user selectable. If you set Pixel input mode to Dual or Quad, the video input can accept two or four pixels per clock, thereby extending the pixel clock rate capability.