DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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10. DisplayPort Source Register Map and DPCD Locations

DisplayPort source instantiations require an embedded controller (Nios II processor or another controller) to act as the policy maker.

Table 9–1 describes the notation used to describe the registers.

Table 61.  Notation

Shorthand

Definition

RW

Read/write

RO

Read only

WO

Write only

CRO

Clear on read or write, read only

CWO

Clear on read or write, write only