DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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10.3.3. DPTX_PRE_VOLT2/DPTX_REG_TXFFE2

These ports drive the respective tx_vod, tx_emp ports (8B/10B channel coding), and tx_reconfig_ffe2 (128B/132B channel coding).

Address: 0x0012

Direction: RW

Reset: 0x00000000

Table 83.  DPTX_PRE_VOLT2/DPTX_REG_TXFFE2 Bits

Bit

Bit Name

Function

31:8

Unused

7:4 TX_FFE2

128B/132B Channel Coding:

Tx FFE Preset on lane 2

3:2

PRE2

8B/10B Channel Coding:

Pre-emphasis output on lane 2

1:0

VOLT2

8B/10B Channel Coding:

Voltage swing output on lane 2