DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022
Public

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11.1.1. DPRX_RX_CONTROL

RECONFIG_LINKRATE drives the rx_reconfig_req . RX_LINK_RATE drives rx_link_rate.

Address: 0x0000

Direction: RW

Reset: 0x00000000

Table 156.  DPRX_RX_CONTROL Bits

Bit

Bit Name

Function

31:30

Unused

29

LQA_ACTIVE
  • 0 = Link Quality Analysis (also known as Post-Link Training Adjust Request) not used
  • 1 = Link Quality Analysis (also known as Post-Link Training Adjust Request) in progress

28

BLACK_VIDEO_EN
  • 0 = Stream 0 receives video output normally
  • 1 = Stream 0 receives video output with all colors set to black

27:24

Unused

23:16

RX_LINK_RATE
Main link rate expressed as multiples of 270 Mbps:
  • 0x06 = 1.62 Gbps
  • 0x0a = 2.7 Gbps
  • 0x14 = 5.4 Gbps
  • 0x1e = 8.1 Gbps
  • 0x01 = 10.0 Gbps
  • 0x02 = 20.0 Gbps

15:14

Unused

 

13

RECONFIG_LINKRATE

This flag always reads back at 0.

1 = Reconfigure the transceiver with link rate RX_LINK_RATE

12

Unused

11 GXB_RESET
  • 0 = Sink transceiver enabled
  • 1 = Sink transceiver reset

10:8

TP

Current training pattern:

8B/10B Channel Coding:

  • 000 = Normal video
  • 001 = Training pattern 1
  • 010 = Training pattern 2
  • 011 = Training pattern 3
  • 111 = Training pattern 4

128B/132B Channel Coding:

  • 000 = Normal video
  • 001 = Training pattern1
  • 010 = Training Pattern 2
  • 011 = Training pattern 2 CDS

7

SCRAMBLER_DISABLE

8B/10B Channel Coding:

  • 0 = Scrambler enabled
  • 1 = Scrambler disabled

128B/132B Channel Coding:

Reserved

6:5

CHANNEL_CODING_SET
  • 0x1 = 8B/10B Channel Coding
  • 0x2 = 128B/132B Channel Coding

4:0

LANE_COUNT

Lane count:

  • 00001 = 1
  • 00010 = 2
  • 00100 = 4