DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 10/20/2022

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Document Table of Contents

4.3.1. Clock Recovery Core

The clock recovery core is a single encrypted module called bitec_clkrec.
Figure 7. Clock Recovery Core Integration DiagramThe figure below shows the integration diagram of the clock recovery core.

To synthesize the video pixel clock from the link clock, the clock recovery core gathers information about the current MSA and the currently used link rate from the DisplayPort sink.

The clock recovery core produces resynchronized video data together with the following clocks:

  • Recovered video pixel clock
  • Second clock with twice the recovered pixel clock frequency

The video output data is synchronous to the recovered video clock. You can use the second clock as a reference clock for the TX transceiver, which is optionally used to serialize the video output data.

Figure 8. Clock Recovery Core Functional DiagramThe following shows a simplified functional diagram of the clock recovery core.

The clock recovery core clocks the video data input gathered from the DisplayPort sink into a dual-clock FIFO at the received video clock speed. The core reads from the video data input using the recovered video clock.

  • Video Timing Generator: This block uses the received MSA to create h-sync , v-sync, and data enable signals that are synchronized to the recovered video clock.
  • Loop Controller: This block monitors the FIFO fill level and regulates its throughput by altering the original Mvid value read from the MSA. The block feeds the modified Mvid to the fPLL Controller, which calculates a set of parameters suitable for the fPLL Controller. This set of parameters provides the value to create a recovered video clock frequency corresponding to the new Mvid value. The calculated fPLL parameters are written by the fPLL Reconfiguration Avalon Master to the fPLL Reconfiguration Controller internal registers.
  • Reconfiguration Controller: This block serializes the parameter values and writes them to the fPLL IP core.
  • fPLL: Generates the recovered video clock and a second clock with twice the frequency.