F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683140
Date 7/14/2022
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Introduction 3. IP Architecture and Functional Description 4. Advanced Features 5. Interfaces 6. Parameters 7. Testbench 8. Troubleshooting/Debugging 9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives 10. Revision History for the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Implementation of Address Translation Services (ATS) in Endpoint Mode C. Packets Forwarded to the User Application in TLP Bypass Mode D. Root Port Enumeration E. Bifurcated Endpoint Support for Independent Resets
2. Introduction x
2.1. Overview 2.2. Features 2.3. Release Information 2.4. Device Family Support 2.5. Performance and Resource Utilization 2.6. IP Core and Design Example Support Levels
3. IP Architecture and Functional Description x
3.1. Architecture 3.2. Functional Description 3.3. Avalon-ST TX/RX 3.4. Interrupts 3.5. Completion Timeout 3.6. Hot Plug 3.7. Power Management 3.8. Configuration Output Interface (COI) 3.9. Configuration Intercept Interface (EP Only) 3.10. Hard IP Reconfiguration Interface 3.11. PHY Reconfiguration Interface 3.12. Page Request Service (PRS) (EP Only)
3.1. Architecture x
3.1.1. Clocks 3.1.2. Refclk 3.1.3. Reset
3.2. Functional Description x
3.2.1. PMA/PCS 3.2.2. Data Link Layer 3.2.3. Transaction Layer
3.3. Avalon-ST TX/RX x
3.3.1. TLP Header and Data Alignment 3.3.2. Avalon-ST RX 3.3.3. Avalon-ST TX 3.3.4. Tag Allocation 3.3.5. Completion Buffer Size
3.3.2. Avalon-ST RX x
3.3.2.1. RX Flow Control
3.3.3. Avalon-ST TX x
3.3.3.1. TX Flow Control
3.4. Interrupts x
3.4.1. Legacy Interrupts 3.4.2. MSI 3.4.3. MSI-X
3.10. Hard IP Reconfiguration Interface x
3.10.1. Configuration Registers Access
3.10.1. Configuration Registers Access x
3.10.1.1. Direct User Avalon-MM Interface (Byte Access) 3.10.1.2. Debug Register Interface Access (Dword Access)
4. Advanced Features x
4.1. Virtualization Support 4.2. TLP Bypass Mode 4.3. Precision Time Measurement (PTM) 4.4. Scalable IOV
4.1. Virtualization Support x
4.1.1. Single Root I/O Virtualization (SR-IOV) 4.1.2. VirtIO
4.1.1. Single Root I/O Virtualization (SR-IOV) x
4.1.1.1. SR-IOV Implementation
4.1.1.1. SR-IOV Implementation x
4.1.1.1.1. Functional Level Reset (FLR)
4.1.2. VirtIO x
4.1.2.1. VirtIO Implementation 4.1.2.2. VirtIO Registers
4.2. TLP Bypass Mode x
4.2.1. Register Settings for TLP Bypass mode 4.2.2. Avalon-MM usage for TLP Bypass Mode 4.2.3. Transmit Interface 4.2.4. Receive Interface 4.2.5. Configuration TLP 4.2.6. Malformed TLP 4.2.7. ECRC
4.2.1. Register Settings for TLP Bypass mode x
4.2.1.1. TLPBYPASS_ERR_EN (Address 0x14194) 4.2.1.2. TLPBYPASS_ERR_STATUS (Address 0x14190)
5. Interfaces x
5.1. Overview 5.2. Clocks and Resets 5.3. Serial Data Interface 5.4. Avalon-ST Interface 5.5. Interrupt Interface 5.6. Hard IP Status Interface 5.7. Error Interface 5.8. 10-bit Tag Support Interface 5.9. Completion Timeout Interface 5.10. Power Management Interface 5.11. Hot Plug Interface (RP Only) 5.12. Configuration Output Interface 5.13. Configuration Intercept Interface (EP Only) 5.14. Hard IP Reconfiguration Interface 5.15. PHY Reconfiguration Interface 5.16. Page Request Service (PRS) Interface (EP Only) 5.17. FLR Interface Signals 5.18. PTM Interface Signals 5.19. VF Error Flag Interface Signals 5.20. VirtIO PCI Configuration Access Interface Signals
5.4. Avalon-ST Interface x
5.4.1. Avalon-ST RX Interface Signals 5.4.2. Avalon-ST TX Interface Signals
5.5. Interrupt Interface x
5.5.1. Legacy Interrupt Interface Signals 5.5.2. MSI Pending Bits Interface Signals
6. Parameters x
6.1. Top-Level Settings 6.2. Core Parameters
6.2. Core Parameters x
6.2.1. Avalon Parameters 6.2.2. Base Address Registers 6.2.3. PCI Express and PCI Capabilities Parameters 6.2.4. Device Identification Registers 6.2.5. Configuration, Debug and Extension Options
6.2.3. PCI Express and PCI Capabilities Parameters x
6.2.3.1. Device Capabilities 6.2.3.2. Link Capabilities 6.2.3.3. Legacy Interrupt Pin Register 6.2.3.4. MSI Capabilities 6.2.3.5. MSI-X Capabilities 6.2.3.6. Slot Capabilities 6.2.3.7. Latency Tolerance Reporting (LTR) 6.2.3.8. Process Address Space ID (PASID) 6.2.3.9. Device Serial Number Capability 6.2.3.10. Page Request Service (PRS) 6.2.3.11. Access Control Service (ACS) Capabilities 6.2.3.12. Power Management 6.2.3.13. Vendor Specific Extended Capability (VSEC) Registers 6.2.3.14. Precision Time Measurement (PTM) 6.2.3.15. Address Translation Services (ATS) 6.2.3.16. TLP Processing Hints (TPH) 6.2.3.17. VirtIO Parameters
7. Testbench x
7.1. FASTSIM Mode Support 7.2. Generating Tile Files 7.3. Endpoint Testbench 7.4. Test Driver Module 7.5. Root Port BFM 7.6. BFM Procedures and Functions
7.5. Root Port BFM x
7.5.1. BFM Memory Map 7.5.2. Configuration Space Bus and Device Numbering 7.5.3. Configuration of Root Port and Endpoint 7.5.4. Issuing Read and Write Transactions to the Application Layer
7.6. BFM Procedures and Functions x
7.6.1. ebfm_barwr Procedure 7.6.2. ebfm_barwr_imm Procedure 7.6.3. ebfm_barrd_wait Procedure 7.6.4. ebfm_barrd_nowt Procedure 7.6.5. ebfm_cfgwr_imm_wait Procedure 7.6.6. ebfm_cfgwr_imm_nowt Procedure 7.6.7. ebfm_cfgrd_wait Procedure 7.6.8. ebfm_cfgrd_nowt Procedure 7.6.9. BFM Configuration Procedures 7.6.10. BFM Shared Memory Access Procedures 7.6.11. BFM Log and Message Procedures 7.6.12. Verilog HDL Formatting Functions
7.6.9. BFM Configuration Procedures x
7.6.9.1. ebfm_cfg_rp_ep Procedure 7.6.9.2. ebfm_cfg_decode_bar Procedure
7.6.10. BFM Shared Memory Access Procedures x
7.6.10.1. Shared Memory Constants 7.6.10.2. shmem_write Task 7.6.10.3. shmem_read Function 7.6.10.4. shmem_display Verilog HDL Function 7.6.10.5. shmem_fill Procedure 7.6.10.6. shmem_chk_ok Function
7.6.11. BFM Log and Message Procedures x
7.6.11.1. ebfm_display Verilog HDL Function 7.6.11.2. ebfm_log_stop_sim Verilog HDL Function 7.6.11.3. ebfm_log_set_suppressed_msg_mask Task 7.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 7.6.11.5. ebfm_log_open Verilog HDL Function 7.6.11.6. ebfm_log_close Verilog HDL Function
7.6.12. Verilog HDL Formatting Functions x
7.6.12.1. himage1 7.6.12.2. himage2 7.6.12.3. himage4 7.6.12.4. himage8 7.6.12.5. himage16 7.6.12.6. dimage1 7.6.12.7. dimage2 7.6.12.8. dimage3 7.6.12.9. dimage4 7.6.12.10. dimage5 7.6.12.11. dimage6 7.6.12.12. dimage7
8. Troubleshooting/Debugging x
8.1. Hardware 8.2. Debug Toolkit
8.1. Hardware x
8.1.1. Debugging Link Training Issues 8.1.2. Debugging Data Transfer and Performance Issues
8.1.1. Debugging Link Training Issues x
8.1.1.1. Generic Tools and Utilities 8.1.1.2. SignalTapII Logic Analyzer 8.1.1.3. Additional Debug Tools
8.1.1.3. Additional Debug Tools x
8.1.1.3.1. Using the Hard IP Reconfiguration Interface 8.1.1.3.2. Enable and Read LCRC and ECRC Error Count
8.1.2. Debugging Data Transfer and Performance Issues x
8.1.2.1. Advanced Error Reporting (AER) 8.1.2.2. Second-Level Debug Tools
8.2. Debug Toolkit x
8.2.1. Overview 8.2.2. Enabling the F-Tile Debug Toolkit 8.2.3. Launching the F-Tile Debug Toolkit 8.2.4. Using the F-Tile Debug Toolkit 8.2.5. Using the F-Tile Link Inspector
8.2.4. Using the F-Tile Debug Toolkit x
8.2.4.1. Main View 8.2.4.2. Toolkit Parameters 8.2.4.3. Channel Parameters 8.2.4.4. Eye Viewer
8.2.4.2. Toolkit Parameters x
8.2.4.2.1. F-Tile Information 8.2.4.2.2. Event Counter 8.2.4.2.3. P0/P1 Configuration Space
8.2.4.3. Channel Parameters x
8.2.4.3.1. General PHY 8.2.4.3.2. TX Path 8.2.4.3.3. RX Path
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Configuration Space Registers for Virtualization A.3. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Configuration Space Registers for Virtualization x
A.2.1. SR-IOV Virtualization Extended Capabilities Registers Address Map A.2.2. PCIe Configuration Registers for Each Virtual Function
A.2.2. PCIe Configuration Registers for Each Virtual Function x
A.2.2.1. Alternative Routing ID (ARI) Capability Structure A.2.2.2. TLP Processing Hint (TPH) Capability Structure A.2.2.3. Address Translation Services (ATS) Capability Structure A.2.2.4. Access Control Services (ACS) Capability Structure
A.2.2.1. Alternative Routing ID (ARI) Capability Structure x
A.2.2.1.1. ARI Enhanced Capability Header Register (Offset 0x0) A.2.2.1.2. ARI Capability and Control Register (Offset 0x4)
A.2.2.2. TLP Processing Hint (TPH) Capability Structure x
A.2.2.2.1. TPH Requester Enhanced Capability Header (Offset 0x0) A.2.2.2.2. TPH Requester Capability Register (Offset 0x4) A.2.2.2.3. TPH Requester Control Register (Offset 0x8)
A.2.2.3. Address Translation Services (ATS) Capability Structure x
A.2.2.3.1. ATS Enhanced Capability Header (Offset 0x0) A.2.2.3.2. ATS Capability Register and ATS Control Register (Offset 0x4)
A.2.2.4. Access Control Services (ACS) Capability Structure x
A.2.2.4.1. ACS Extended Capability Header (Offset 0x0) A.2.2.4.2. ACS Capability Register (Offset 0x4) A.2.2.4.3. ACS Control Register (Offset 0x6) A.2.2.4.4. Egress Control Vector (Offset 0x8)
A.3. Intel-Defined VSEC Capability Registers x
A.3.1. Intel-Defined VSEC Capability Header (Offset 00h) A.3.2. Intel-Defined Vendor Specific Header (Offset 04h) A.3.3. Intel Marker (Offset 08h) A.3.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.3.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.3.6. General Purpose Control and Status Register (Offset 0x30) A.3.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.3.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.3.9. Correctable Internal Error Status Register (Offset 0x3C) A.3.10. Correctable Internal Error Mask Register (Offset 0x40)
B. Implementation of Address Translation Services (ATS) in Endpoint Mode x
B.1. Sending Translated/Untranslated Requests B.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) B.3. Invalidating Requests/Completions
C. Packets Forwarded to the User Application in TLP Bypass Mode x
C.1. EP TLP Bypass Mode (Upstream) C.2. RC TLP Bypass Mode (Downstream)
E. Bifurcated Endpoint Support for Independent Resets x
E.1. PCI Express Resets E.2. Supported Configurations
E.2. Supported Configurations x
E.2.1. Configuration Type A E.2.2. Configuration Type B E.2.3. Configuration Type C
1. Acronyms
2. Introduction
3. IP Architecture and Functional Description
4. Advanced Features
5. Interfaces
6. Parameters
7. Testbench
8. Troubleshooting/Debugging
9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide Archives
10. Revision History for the F-Tile Avalon Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Implementation of Address Translation Services (ATS) in Endpoint Mode
C. Packets Forwarded to the User Application in TLP Bypass Mode
D. Root Port Enumeration
E. Bifurcated Endpoint Support for Independent Resets

3.7. Power Management

Software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management output signals indicate the current power state. The IP core supports the two mandatory power states: D0 (full power) and D3 (preparation for a loss of power). It does not support the optional D1 and D2 low power states.

The correspondence between the device power states (D states) and link power states (L states) is as follows:
Table 20.  Device and Link Power States Relationship
Device Power State Link Power State
D0 L0
D1 (not supported) L1
D2 (not supported) L2
D3 L1, L2/L3 Ready

The F-Tile Avalon Streaming Intel FPGA IP for PCI Express IP core supports the required D0 and D3 Power Management states. It does not support the optional D1 and D2 Power Management states. The software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management interface transmits the D-state to the Application Layer.

Endpoint D3 Entry

  1. The power management software must ensure that all outstanding non-posted request have received their associated completions by polling that Transaction Pending bit in the Device Status register. Only then, it can put a function into D3hot state by writing the appropriate value into the PowerState field of its Power Management Control and Status Register.
  2. The link is forced to L1 state when the function changes to D3hot state. In this state, the function can only initiate PME or PME_TO_ACK Messages and can only respond to configuration request or the PME_Turn_Off Message.
  3. The power management software sends the PME_Turn_Off Message to the Endpoint to initiate power down. The delivery of the message TLP causes the link to transition to L0 and the Message is also passed on to the Avalon-ST RX interface.
  4. The IP core auto transmits a PME_TO_Ack Message to acknowledge the Turn Off request.
  5. When ready for power removal D3cold, the application logic in Endpoint asserts p#_app_ready_entr_l23_i. The IP core then sends the PM_Enter_L23 DLLP and initiates the Link transition to L23 Ready.
  6. The reference clock and power can finally be removed when the link has transitioned to the L23 Ready state. The link then enters L3 state if auxiliary power VAUX is not detected or the p#_sys_aux_pwr_det_i signal is de-asserted. If the reference clock and power are not turned off and the p#_sys_aux_pwr_det_i signal is asserted, the link enters L2 state.
Figure 34. Link transition to L2/L3 Ready

Endpoint D3 Exit

  1. Endpoint L1 Exit:
    • Host initiate: Power management software can write to the PowerState field of the function’s Power Management Control and Status (PMCSR) register to change its PM state to D0. Alternatively, the host can initiate link retrain, link disable or hot reset for L1 exit.
    • Device Initiate: For the Endpoint to exit the D3 state, the PME_en bit in the (PMCSR) register needs to be set first. TheApplication Layer can then request a wake-up event by asserting apps_pm_xmt_pme_i, which causes the IP core to transmit a PM_PME Message. In addition, the IP core sets the PME_status bit in the PMCSR register to notifysoftware that it has requested the wake-up. The PCIe Link states are indicated on the power management interface. The LTSSM state is indicated on the ltssm_stateoutput.
  2. Endpoint L2 Exit: The host system or root port transits into Detect link state and starts to send Electrical Idle order set upon power-up. When the endpoint receives Electrical Idle order set during the L2 link state, it triggers a reset to the PCIe IP core before transit in to Detect link state.
  3. Endpoint L3 Exit: A power cycle to FPGA is required to exit L3 state.
Figure 35. Application Layer requests a wake-up event by asserting apps_pm_xmt_pme_i
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