F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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Document Table of Contents

5.13. Configuration Intercept Interface (EP Only)

Table 75.  Configuration Intercept Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_cii_req_o Output EP coreclkout_hip

Note: Not available for p2 and p3.

Indicates the CFG request is intercepted and all the other CII signals are valid.

p#_cii_hdr_poisoned_o Output EP coreclkout_hip

Note: Not available for p2 and p3.

The poisoned bit in the received TLP header on the CII.

p#_cii_hdr_first_be_o[3:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

The first dword byte enable field in the received TLP header on the CII.

p#_cii_func_num_o[2:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

The function number in the received TLP header on the CII.

Applicable when multiple Physical Functions are enabled

p#_cii_wr_o Output EP coreclkout_hip

Note: Not available for p2 and p3.

Indicates that cii_dout_o is valid. This signal is asserted only for a configuration write request.

p#_cii_addr_o[9:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

The double word register address in the received TLP header on the CII.

p#_cii_dout_o[31:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

Received TLP payload data from the link partner to your application client. The data is in little endian format. The first received payload byte is in [7:0].

p#_cii_override_en_i Input EP coreclkout_hip

Note: Not available for p2 and p3.

Override enable. When the application logic asserts this input, the PCIe Hard IP overrides the CfgWr payload or CfgRd completion using the data supplied by the application logic on cii_override_din.

p#_cii_override_din_i[31:0] Input EP coreclkout_hip

Note: Not available for p2 and p3.

Override data.
  • CfgWr: override the write data to the PCIe Hard IP register with data supplied by the application logic on cii_override_din.
  • CfgRd: override the data payload of the completion TLP with data supplied by the application logic on cii_override_din.
p#_cii_halt_i Input EP coreclkout_hip

Note: Not available for p2 and p3.

Flow control input signal. When cii_halt_i is asserted, the PCIe Hard IP halts the processing of CFG requests for the PCIe configuration space registers.

p#_cii_wr_vf_active_o Output EP coreclkout_hip

Note: Not available for p2 and p3.

Indicating the Cfg TLP is targeting a VF. Applicable when SRIOV is enabled.

p#_cii_vf_num_o[6:0] Output EP coreclkout_hip

Note: Not available for p2 and p3.

The VF number that this Cfg TLP is targeted. Valid when cii_func_active_o is asserted.

Applicable when SRIOV is enabled.

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