F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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5.11. Hot Plug Interface (RP Only)

Table 73.  Hot Plug Interface Signals
Signal Name Direction EP/RP/BP Clock Domain Description
p#_sys_atten_button_pressed_i Input RP coreclkout_hip Attention Button Pressed. Indicates that the system attention button was pressed, and sets the Attention Button Pressed bit in the Slot Status Register.
p#_sys_pwr_fault_det_i Input RP coreclkout_hip Power Fault Detected. Indicates the power controller detected a power fault at this slot.
p#_sys_mrl_sensor_chged_i Input RP coreclkout_hip MRL Sensor Changed. Indicates that the state of the MRL sensor has changed.
p#_sys_pre_det_chged_i Input RP coreclkout_hip Presence Detect Changed. Indicates that the state of the card presence detector has changed.
p#_sys_cmd_cpled_int_i Input RP coreclkout_hip Command Completed Interrupt. Indicates that the Hot Plug controller completed a command.
p#_sys_pre_det_state_i Input RP coreclkout_hip

Indicates whether or not a card is present in the slot.

0 : slot is empty.

1 : card is present in the slot.

p#_sys_mrl_sensor_state_i Input RP coreclkout_hip

MRL Sensor State. Indicates the state of the manually operated retention latch (MRL) sensor.

0 : MRL is closed.

1 : MRL is open.

p#_sys_eml_interlock_engaged_i Input RP coreclkout_hip Indicates whether the system electromechanical interlock is engaged, and controls the state of the electromechanical interlock status bit in the Slot Status Register.

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