F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022

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Document Table of Contents

E.1. PCI Express Resets

For a definition of the types of PCI Express Conventional Reset (including Fundamental Reset), refer to Section 6.6.1 of the PCI Express Base Specification Revision 5.0 Version 1.0. However, the description of warm reset leaves the generation of this reset mechanism as undefined within the base specification. The CEM form factor specification (Section 2.2) further defines an auxiliary signal, named PERST#, as a signal indicating that 3.3V and 12V power supplies are within specified voltage tolerances. PERST# may later assert in advance of the power being switched off in S3/S4/S5 system sleep states.

The PERST# signal is used to indicate when the power supply is within its specified voltage tolerance and is stable. It also initializes a component’s state machines and other logic once power supplies stabilize. On power-up, the de-assertion of PERST# is delayed 100 ms (TpvpERL) from the power rails achieving specified operating limits. Also, within this time, the reference clocks (REFCLK+, REFCLK-) also become stable, at least TPERST-CLK before PERST# is de-asserted. PERST# is asserted in advance of the power being switched off in a power-managed state like S3. PERST# is asserted when the power supply is powered down, but without the advanced warning of the transition.

The CEM specification describes PERST# as a power-stable indicator indicative of a cold-reset. Once again, PERST# is intended to be a globally distributed signal to all system components and adapters and can be used to reset a component to its initial conditions.

In a typical system, the in-band conventional reset mechanism (Hot Reset) can be used to return a specific component or tier of downstream components behind a given Root Port back to initial conditions, under a software-controlled mechanism (Secondary Bus reset bit). This mechanism can be used to reset portions of the PCIe hierarchy, and requires that PERST# is not cycled, and power not removed from a given component. This Hot Reset mechanism is the preferred mechanism to issue independent conventional reset to different F-Tile endpoints residing in the same component and/or adapter.

This Appendix describes how you can use a bifurcated two-endpoint configuration of F-Tile connected to independent systems/hosts.

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