F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.2.3. Transmit Interface

All TLPs transmitted by the application through the TX streaming interface are sent out as-is, without any tracking for completion. The F-Tile AVST IP for PCIe does not perform any check on the TLPs. User application logic is responsible for sending TLPs that comply with the PCIe specifications.

Did you find the information on this page useful?

Characters remaining:

Feedback Message