F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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5.2. Clocks and Resets

Table 58.  Clock Signals
Signal Name Direction EP/RP/BP Description
coreclkout_hip Output EP/RP/BP

This clock drives the application layer. Clock freq depends on data-rate and number of lanes being use.

Gen3 : 250 MHz

Gen4 : 350 MHz / 400 MHz / 450 MHz / 500 MHz for Intel® Agilex™

refclk0 Input EP/RP/BP

Input reference clock for 1x16, 1x8 or 1x4 mode. Connect outrefclk_fgt_i (i = 0 to 7) from “F-Tile Reference and SystemPLL Clocks” IP to this port.

refclk1 Input EP/RP/BP

Separate refclk for 2x8, 2x4 or 4x4 mode. Drive this input with the same clock for refclk0 input port if your design does not need a separate refclk. Connect outrefclk_fgt_i (i = 0 to 7) from “F-Tile Reference and SystemPLL Clocks” IP to this port.

refclk2 Input EP/RP/BP

Separate refclk for 4x4 mode only. Drive this input with the same clock for refclk0 input port if your design does not need a separate refclk. Connect outrefclk_fgt_i (i = 0 to 7) from “F-Tile Reference and SystemPLL Clocks” IP to this port.

refclk3 Input EP/RP/BP

Separate refclk for 4x4 mode. Drive this input with the same clock for refclk0 input port if your design does not need a separate refclk. Connect outrefclk_fgt_i (i = 0 to 7) from “F-Tile Reference and SystemPLL Clocks” IP to this port.

pcie_systempll_clk Input EP/RP/BP

System PLL clock from “F-tile Reference and SystemPLL Clocks” IP.

Connect out_systempll_clk_0 from the "F-Tile Reference and System PLL Clocks" IP to this port.

For Mode of System PLL setting, select frequency that is TWO times of the selected PLD Clock Frequency. For example, if the selected PLD clock frequency is 500 MHz, use the "PCIE_FREQ_1000" setting.

For Refclk source, select any of the enabled Refclk. Refer to Refclk for more information.

p#_hip_reconfig_clk Input EP/RP/BP

Clock for hip_reconfig interface. Frequency ranges from 50 MHz to 125 MHz.

Note: Intel recommends using 100 MHz clock source for HIP reconfig clock
xcvr_reconfig_clk Input EP/RP/BP

Clock for PHY reconfiguration interface. Frequency ranges from 50 MHz to 125 MHz.

Note: Intel recommends using 100 MHz clock source for PHY reconfig clock
Table 59.  Reset SignalsNote: 'n' indicates active low signal
Signal Name Direction EP/RP/BP Clock Domain Description
pin_perst_n Input EP/RP/BP Async

This is an active-low input to PCIe Hard IP for PERST# function defined by PCIe specification

p#_pin_perst_n Output EP/RP/BP Async

PERST# status indication for port#.

When Independent Perst is enabled, assertion of this signal is delayed for port# controlled by gpio_perst.

ninit_done Input EP/RP/BP Async

From “Reset Release IP”.

A “1” on this active-low signal indicates that the FPGA device is not yet fully configured.

A “0” indicates the device has been configured and is in normal operating mode.

p#_reset_status_n Output EP/RP/BP coreclkout_hip

Held low until PCIe port is out of reset.

i_gpio_perst#_n Input EP/BP async This is an active-low reset to each port when Independent Perst option is enabled.

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