F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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E.2.1. Configuration Type A

Port 0, Port 1 and System Clock obtain free running clock. When PERST# is asserted from Host0 or Host1, the reference clock is not removed.

You have the option to:
  • Shared Port0 RefClk, Port1 RefClk or SysPLL RefClk to the same reference clock pin depending on user selection
  • Map Port0 RefClk, Port1 RefClk or SysPLL RefClk to individual reference clock pin where the free running clock is provided from the Host card.

Variations of free running clock source is illustrated in the diagrams below.

Figure 96. 2 Host with free running clock from the FPGA clock generator
Note: For this configuration Port 0 RefClk, Port 1 RefClk and SysPLL RefClk can be shared to a reference clock pin
Figure 97. 2 Host with free running clock from Host
Note: Free running clock is supplied by the Host system
Figure 98. 2 Host with free running clock (Port 0 as primary port and in SRIS/SRNS mode)

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