F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022

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Document Table of Contents Eye Viewer

Note: The Eye Viewer feature is not currently supported. This feature may be enabled in a future release of the Intel® Quartus® Prime Pro Edition software.

The F-Tile Debug Toolkit supports the Eye Viewer tool that allows you to measure the eye height margin for each channel.

Note: The F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Eye Viewer feature of the Debug Toolkit does not support independent error sampler for performing eye margining performed on the actual data path. As a result, eye margining may produce uncorrectable errors in the data stream and cause the LTSSM to go to the Recovery state. You may mask out all errors (example AER registers) while performing eye margining and reset all error counters, error registers etc. after margining gets completed.

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