F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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2.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the Avalon® -ST IP core supports.

Table 5.   Intel® Agilex™ Recommended FPGA Fabric Speed Grades for All Avalon-ST Widths and FrequenciesThe recommended FPGA fabric speed grades are for production parts.

Lane Rate

Link Configuration

Application Interface Data Width

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Gen4 1 x16 512-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz -1,-2
450 MHz / 400 MHz / 350 MHz / 225 MHz / 200 MHz / 175 MHz -3
1 x8 256-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
2 x8

512-bit 1

250 MHz / 225 MHz / 200 MHz / 175 MHz -1,-2
225 MHz / 200 MHz / 175 MHz -3
256-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz / 250 MHz / 225 MHz / 200 MHz / 175 MHz -1,-2
450 MHz / 400 MHz / 350 MHz / 225 MHz / 200 MHz / 175 MHz -3
1x4 128-bit 500 MHz/ 450 MHz / 400 MHz /350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
2 x4 128-bit 500 MHz/ 450 MHz / 400 MHz / 350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
4 x4 128-bit 500 MHz / 450 MHz / 400 MHz / 350 MHz -1,-2
450 MHz / 400 MHz / 350 MHz -3
Gen3 1 x16 512-bit 250 MHz -1,-2,-3

256-bit 2

250 MHz -1,-2,-3
1 x8 256-bit 250 MHz -1,-2,-3
2 x8 256-bit 250 MHz -1,-2,-3
1 x4 128-bit 250 MHz -1,-2,-3
2 x4 128-bit 250 MHz -1,-2,-3
4 x4 128-bit 250 MHz -1,-2,-3
Note: Select the highest clock frequency to achieve maximum PCIe Gen4 bandwidth.

The following table shows the typical resource utilization information for selected configurations.

The resource usage is based on the Avalon® -ST IP core top-level entity (intel_pcie_ftile_ast) that includes IP core soft logic implemented in the FPGA fabric.

Table 6.  Resource Utilization Information of the IP
IP Configuration Device Family ALMs M20Ks Logic Registers
Gen4 x16, EP Intel Agilex 7461 11 14,845
Gen4 x16, RP Intel Agilex 7462 11 15,032
Gen4 x8x8, EP Intel Agilex 7605 11 15,331
Gen4 x8, EP Intel Agilex 5844 11 10,822
Gen4 x8, RP Intel Agilex 5857 11 10,898
Gen4 x4, EP Intel Agilex 5327 11 9,499
Gen4 x4x4, RP Intel Agilex 6717 11 12,668
Gen4 x4x4x4x4, RP Intel Agilex 9326 11 18,823
Note: The default IP parameter is used for each of the IP configurations above, resource utilization may increase as additional IP features enabled. The resource utilization of the IP above has taken the tile logic into account.

1 In this configuration, interface width increased to support lower application clock frequency.
2 In this configuration, interface efficiency is traded off for lower interface width.

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