F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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4.2.7. ECRC

In TLP bypass mode, the ECRC is not generated or stripped by the F-Tile Avalon-ST IP for PCIe (i.e. you need to insert and check ECRC if it is required, and this is done by appending ECRC to the payload and set TD field in the Header).

ECRC generation and checking/stripping are done by PCIe Controller within the F-Tile for non-TLP bypass mode.

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