F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 7/14/2022
Public

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3.2.1. PMA/PCS

The PMA and PCS blocks handles the PHY packets. The PMA receives and transmits high-speed serial data on the serial lanes. The PCS acts as an interface between PMA and PCIe controller and performs functions like data encoding and decoding, scrambing and descrambling, block synchronization etc. The PCIe PCS in F-tile is based on PHY Interface for PCIe Express (PIPE) Base Specification 4.4.1.

The PMA consists of up to four FGT quads. Each quad contains four FGT SerDes lanes and each FGT SerDes lane contains two transmit PLLs.. The transmit PLLs generate the required transmit clocks for Gen1/Gen2/Gen3/Gen4 speeds. For x16 and x8 mode which require x16 and x8 lane widths across more than one quad, one of the quads acts as the master PLL source to drive the clock inputs for the lanes in the other quads. The FGT SerDes lane assignment for x16, x8, and x4 modes is shown in the table below.

The PMA performs functions such as serialization/deserialization, clock data recovery, and analog front-end functions such as Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE) and transmit equalization. For more information about FGT SerDes, please refer to the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide.

Table 12.  PHY Channel Assignement per Bifurcation Mode
Bifurcation Mode Port 0 (x16) Port 1 (x8) Port 2 (x4) Port 3 (x4)
1 x16 0-15 NA N/A N/A
2 x 8 0-7 8-15 N/A N/A
4 x 4 0-3 8-11 4-7 12-15

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